Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator

The demand for higher data rates in receivers with carrier aggregation (CA) such as LTE, increases the efforts to integrate large number of wireless services into single receiving path, so it needs to digitize the signal in intermediate or high frequencies. It relaxes most of the front-end blocks but makes the design of ADC very challenging. Solving the bottleneck associated with ADC in receiver architecture is a major focus of many ongoing researches. Recently, continuous time Sigma-Delta analog-to-digital converters (ADCs) are getting more attention due to their inherent filtering properties, lower power consumption and wider input bandwidth. But, it suffers from several non-idealities such as clock jitter and ELD which decrease the ADC performance. This dissertation presents two projects that address CT-ΣΔ modulator non-idealities. One of the projects is a CT- ΣΔ modulator with 10.9 Effective Number of Bits (ENOB) with Gradient Descent (GD) based calibration technique. The GD algorithm is used to extract loop gain transfer function coefficients. A quantization noise reduction technique is then employed to improve the Signal to Quantization Noise Ratio (SQNR) of the modulator using a 7-bit embedded quantizer. An analog fast path feedback topology is proposed which uses an analog differentiator in order to compensate excess loop delay. This approach relaxes the requirements of the amplifier placed in front of the quantizer. The modulator is implemented using a third order loop filter with a feed-forward compensation paths and a 3-bit quantizer in the feedback loop. In order to save power and improve loop linearity a two-stage class-AB amplifier is developed. The prototype modulator is implemented in 0.13μm CMOS technology, which achieves peak Signal to Noise and Distortion Ratio (SNDR) of 67.5dB while consuming total power of 8.5-mW under a 1.2V supply with an over sampling ratio of 10 at 300MHz sampling frequency. The prototype achieves Walden's Figure of Merit (FoM) of 146fJ/step. The second project addresses clock jitter non-ideality in Continuous Time Sigma Delta modulators (CT- ΣΔM), the modulator suffer from performance degradation due to uncertainty in timing of clock at digital-to-analog converter (DAC). This thesis proposes to split the loop filter into two parts, analog and digital part to reduce the sensitivity of feedback DAC to clock jitter. By using the digital first-order filter after the quantizer, the effect of clock jitter is reduced without changing signal transfer function (STF). On the other hand, as one pole of the loop filter is implemented digitally, the power and area are reduced by minimizing active analog elements. Moreover, having more digital blocks in the loop of CT- ΣΔM makes it less sensitive to process, voltage, and temperature variations. We also propose the use of a single DAC with a current divider to implement feedback coefficients instead of two DACs to decrease area and clock routing. The prototype is implemented in TSMC 40 nm technology and occupies 0.06 mm^2 area; the proposed solution consumes 6.9 mW, and operates at 500 MS/s. In a 10 MHz bandwidth, the measured dynamic range (DR), peak signal-to-noise-ratio (SNR), and peak signal-to-noise and distortion (SNDR) ratios in presence of 4.5 ps RMS clock jitter (0.22% clock period) are 75 dB, 68 dB, and 67 dB, respectively. The proposed structure is 10 dB more tolerant to clock jitter when compared to the conventional ΣΔM design for similar loop filter

IEEE Transactions on Biomedical Circuits And Systems: Vol. 7, No. 4, Agustus 2013

1. Exploiting jump-resonance hysteresis in silicon auditory front-ends for extracting speaker discriminative formant trajectories / K. Aono, R. K. Shaga, S. Chakrabartty 2. A Bispectral approach to analyze nonlinear cochlear active mechanisms in transient evoked otoacoustic emissions / S. Marchesi, G. Tognola, A. Paglialonga 3. Making use of auditory models for better mimicking of normal hearing processes with cochlear implants: The SAM coding strategy / T. Harczos, A. Chillian, P. Husar 4. Design of wavelet-based ECG detector for implantable cardiac pacemakers / Y. -J. Min. H. -K. Kim, Y. -R. Kang, G. -S. Kim, J. Park, S. -W. Kim 5. An Ultra-linear piezo-floating-gate strain-gauge for self-powered measurement of quasi-static-strain / P. Sarkar, C. Huang, S. Chakrabartyy 6. FAST: A Framework for simulation and analysis of large-scale protein-silicon biosensor circuits / M. Gu, S. Chakrabartyy 7. Reconfigurable bioimpedance emulation system for electrical impedance tomography system validation / N. Li, H. Xu, Z. Zhou, J. Xin, Z. Sun, X. Xu 8. A Zero-voltage switching technique for minimizing the current-source power of implanted stimulators / U. Cilingiroglu, S. Ipek 9. A Switched-capacitor front-end for velocity-selective ENG recording / R. Rieger, J. Taylor 10. Real-time prediction of neuronal population spiking activity using FPGA / W. X. Y. Li, R. C. C. Cheung, R. H. M. Chan, D. Song, T. W. Berger 11. A Low-power configurable neural recording system for epileptic seizure detection / C. Qian, J. Shi, J. Parramon, E. Sanchez-Sinencio Etc